Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
US7986570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2009 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Nov 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.