Systems and methods for selecting wafer processing order for cyclical two pattern defect detection
US7987014B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2008 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | May 26, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method of sequencing wafer processing order to minimize sequence correlation in a cyclical two pattern model by generating a set of sequences of wafer identifiers that each specify an order by which one or more fabrication equipments processes wafers of a wafer lot, where the wafer lot contains a number of slots and the fabrication equipments each includes a first subsystem for processing wafers in odd-numbered slots of the first wafer lot and a second subsystem for processing wafers in even-numbered slots of the first wafer lot, and where each of the generated wafer sequences contains exactly a number of wafer identifiers that match the wafer identifiers in every other wafer sequence indexed in the set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.