Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits
US7987382B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2006 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Feb 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may, for example, be the introduction of ground bounce by switching of the other digital sub-circuit. Another inventive aspect relates to an at least partially digital circuit comprising such a digital sub-circuit for minimizing the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.