Interposer for connecting plurality of chips and method for manufacturing the same
US7987588B2 · kind B2 · utility
0Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2008 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Feb 17, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.