Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate
US7989306B2 · kind B2 · utility
11Cited by
10References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Sep 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.