Integrated capacitors in package-level structures, processes of making same, and systems containing same
US7989916B2 · kind B2 · utility
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13References
22Claims
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Key dates
| Filing date | Nov 10, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Nov 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.