Delay locked loop circuit of semiconductor device
US7990785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2008 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jan 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.