Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system
US7991979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2008 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jan 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to identifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.