Method of placing and routing for power optimization and timing closure
US7992122B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2005 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jul 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and/or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.