Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US7996625B2 · kind B2 · utility
7Cited by
98References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Jun 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.