Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache
US7996644B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Apr 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A resource within a microprocessor sharing access to a cache is assigned a static portion of the cache and a dynamic portion. The resource is blocked from victimizing static portions assigned to other resources, yet, allowed to victimize the static portion assigned to the resource and the dynamically shared portion. If the resource does not access the cache enough times over a period of time, the static portion assigned to the resource is reassigned to the dynamically shared portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.