Floating point status/control register encodings for speculative register field
US7996662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2005 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Apr 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.