Wei-Han Lien
35Patents
9h-index
52Co-inventors
78Inventor score
Filing activity: Jan 3, 2000 → Aug 22, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6622237B1 | Store to load forward predictor training using delta tag | Physics | 32 | Expired |
| US6694424B1 | Store load forward predictor training | Physics | 32 | Expired |
| US9304573B2 | Dynamic voltage and frequency management based on active processors | Emerging Cross-Sectional Technologies | 24 | Active |
| US8219787B2 | Early release of resources by proceeding to retire store operations from exception reporting stage but keeping in load/store queue | Physics | 20 | Active |
| US7996662B2 | Floating point status/control register encodings for speculative register field | Physics | 20 | Active |
| US6651161B1 | Store load forward predictor untraining | Physics | 19 | Expired |
| US8352685B2 | Combining write buffer with dynamically adjustable flush metrics | Physics | 12 | Active |
| US9541984B2 | L2 flush and memory fabric teardown | Emerging Cross-Sectional Technologies | 9 | Active |
| US9703354B2 | Dynamic voltage and frequency management based on active processors | Emerging Cross-Sectional Technologies | 9 | Active |
| US7472260B2 | Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion | Physics | 7 | Active |
| US9383806B2 | Multi-core processor instruction throttling | Emerging Cross-Sectional Technologies | 5 | Active |
| US7426216B2 | Advanced telecommunications router and crossbar switch controller | Electricity | 5 | Expired |
| US10303238B2 | Dynamic voltage and frequency management based on active processors | Emerging Cross-Sectional Technologies | 5 | Active |
| US9411360B2 | Method to manage current during clock frequency changes | Emerging Cross-Sectional Technologies | 3 | Active |
| US7373486B2 | Partially decoded register renamer | Physics | 2 | Expired |
| US7962730B2 | Replaying memory operation assigned a load/store buffer entry occupied by store operation processed beyond exception reporting stage and retired from scheduler | Physics | 2 | Active |
| US9311100B2 | Usefulness indication for indirect branch prediction training | Physics | 2 | Active |
| US7647518B2 | Replay reduction for power saving | Physics | 2 | Active |
| US9280471B2 | Mechanism for sharing private caches in a SoC | Emerging Cross-Sectional Technologies | 2 | Active |
| US7826477B2 | Advanced telecommunications router and crossbar switch controller | Electricity | 1 | Active |
| US8566528B2 | Combining write buffer with dynamically adjustable flush metrics | Physics | 1 | Active |
| US9626185B2 | IT instruction pre-decode | Physics | 1 | Active |
| US7586911B2 | Method and apparatus for packet transmit queue control | Electricity | 1 | Active |
| US11003233B2 | Dynamic voltage and frequency management based on active processors | Emerging Cross-Sectional Technologies | 0 | Active |
| US9158541B2 | Register renamer that handles multiple register sizes aliased to the same storage locations | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.