Method and apparatus to avoid power transients during a microprocessor test
US7996703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2008 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Apr 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor. The initializing mechanism initializes a timer. The initializing mechanism then sends a clock start command to the microprocessor. The clocks on the microprocessor are started. Upon the clocks starting, the timer begins and allows temporary transients, such as voltage droop due to a large instantaneous change in demand for current due to the commencement of clock switching. Responsive to the timer reaching a target value, an interrupt unit sends a system reset interrupt. Responsive to the interrupt unit sending the system reset interrupt, an instruction fetch unit fetches a first instruction. This operation will be deterministic to the state of the rest of the microprocessor memory elements (latches, arrays, et al.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.