Computer readable medium, system and associated method for designing integrated circuits with loop insertions
US7996808B2 · kind B2 · utility
4Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2008 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Nov 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.