Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program
US7996813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2010 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Mar 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.