Multilayer wiring structure, semiconductor device, pattern transfer mask and method for manufacturing multilayer wiring structure
US7999392B2 · kind B2 · utility
7Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Jun 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region facing the via is locally narrowed in at least the interconnection, facing the via, of the interconnections adjacent to the interconnection connected to the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.