Scan testing architectures for power-shutoff aware systems
US8001433B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2008 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Dec 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318563
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.