Patent · US Active

Characterization and reduction of variation for integrated circuits

US8001516B2 · kind B2 · utility

116Cited by

91References

61Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Taber H. Smith · San Jose, US
Vikas Mehrotra · London, GB
David White · San Jose, US

Key dates

Filing date	Jun 2, 2008
Grant date	Aug 16, 2011
Priority date	—
Expiry date	Aug 28, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.