Fabricating method of vertical transistor
US8003457B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2011 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Mar 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
Abstract
A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and the lower part has a first doped region. A gate dielectric layer is formed on a sidewall at one side of the pillar. A surrounding gate is formed on the gate dielectric layer located on the channel region, and a base line electrically connected to the channel region is formed on a sidewall at the other side of the pillar. A second doped region is formed in the upper part of the pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.