Dual stress liner device and method

US8004035B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventor

• Gaku Sudo · Yokohama, JP

Key dates

• Filing date: Aug 4, 2009
• Grant date: Aug 23, 2011
• Expiry date: Sep 29, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.