Suppression of hot-carrier effects using double well for thin gate oxide LDMOS embedded in HV process
US8004038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2006 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | May 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/514
Abstract
A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.