Static random access memory (SRAM) cell and method for forming same
US8004042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2009 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Mar 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor. The second linear intra-cell connection electrically couples the active area of the second pull-down transistor, the active area of the second pull-up transistor, and the active area of the second pass-gate transistor to a gate electrode of the first pull-down transistor and a gate electrode of the first pull-up transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.