Lead frame based semiconductor package and a method of manufacturing the same
US8004069B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2005 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterised in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.