Patent · US Active

Memory circuit arrangement and method for the production thereof

US8004869B2 · kind B2 · utility

10Cited by

3References

5Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Wolfgang Gruber · Bischofswerda, DE
Ronald Kakoschke · Birkenfeld, DE
Thomas Schweizer · Ebersberg, DE
Dominik Wegertseder · Haar, DE

Key dates

Filing date	May 3, 2010
Grant date	Aug 23, 2011
Priority date	—
Expiry date	May 3, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.