System and method for memory array decoding
US8004926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2009 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Jan 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory blocks. The memory system also includes a bit line decoder and Q×M switch modules. Each Q×M switch module selectively controls access to up to J of the M memory sub-blocks of the Q memory blocks. The Q word line decoders and the bit line decoder access less than M memory sub-blocks in at least two of the Q memory blocks during one of a read and write operation. M and Q are integers greater than 1, and J is an integer greater than or equal to 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.