Processor local bus bridge for an embedded processor block core in an integrated circuit
US8006021B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Sep 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.