Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system
US8006070B2 · kind B2 · utility
7Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Jun 21, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.