Simultaneous speculative threading light mode
US8006073B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Apr 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for management of resource allocation of threads for efficient execution of instructions. Prior to dispatching decoded instructions of a first thread from the instruction fetch unit to a buffer within a scheduler, logic within the instruction fetch unit may determine the buffer is already full of dispatched instructions. However, the logic may also determine that a buffer for a second thread within the core or micro core is available. The second buffer may receive and issue decoded instructions for the first thread until the buffer is becomes unavailable. While the second buffer receives and issues instructions for the first thread, the throughput of the system for the first thread may increase due to a reduction in wait cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.