Patent · US Active

Method for speeding up serial data tolerance testing

US8006141B2 · kind B2 · utility

1Cited by

5References

18Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Samuel G. Stephens · Austin, US
Michael P. Baker · Round Rock, US

Key dates

Filing date	Jun 30, 2009
Grant date	Aug 23, 2011
Priority date	—
Expiry date	Jan 5, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3171
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.