Patent · US Active

Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew

US8006213B2 · kind B2 · utility

4Cited by

16References

13Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Christopher J. Berry · Hudson, US
Jose L. Neves · Poughkeepsie, US
Charlie C. Hwang · Wappingers Falls, US
David W. Lewis · Pleasant Valley, US

Key dates

Filing date	Feb 15, 2008
Grant date	Aug 23, 2011
Priority date	—
Expiry date	Mar 24, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.