Method for optimizing direct wafer bond line width for reduction of parasitic capacitance in MEMS accelerometers
US8007166B2 · kind B2 · utility
1Cited by
17References
12Claims
0Family size
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Key dates
| Filing date | May 24, 2006 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Sep 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01P2015/0828
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device by reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to a water vapor for a predetermined time period and at a first temperature capable of evaporating water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.