Patent · US Expired

Two layer LTO temperature oxide backside seal for a wafer

US8007914B2 · kind B2 · utility

0Cited by

8References

3Claims

0Family size

Assignee

Siltronic AG · DE

Inventors

Jin Li · 安丰镇, CN
Boon-Koon Ow · Singapore, SG

Key dates

Filing date	Sep 18, 2003
Grant date	Aug 30, 2011
Priority date	—
Expiry date	May 8, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/2205
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A two layer LTO backside seal for a wafer. The two layer LTO backside seal includes a low stress LTO layer having a first major side and a second major side, the first major5 side of the low stress LTO layer adjacent to one major side of the wafer. The two layer LTO backside seal further includes a high stress LTO layer having a first major side and second major side, the first major side of the high stress LTO layer adjacent the second major side of the low stress LTO layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.