Method for fabricating 1T-DRAM on bulk silicon
US8008137B2 · kind B2 · utility
20Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2007 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Mar 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.