Patent · US Active

Package including a lead frame, a chip and a sealant

US8008784B2 · kind B2 · utility

3Cited by

2References

17Claims

0Family size

Assignee

ADVANCED SEMICONDUCTOR ENGINEERING, INC. · TW

Inventors

Young-Moon Hong · Seojong-myeon, KR
Chang Suk Han · Ansan-si, KR
Chang Won Park · Suwon-si, KR

Key dates

Filing date	Oct 2, 2008
Grant date	Aug 30, 2011
Priority date	—
Expiry date	Aug 8, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/01078
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A package and a fabricating method thereof are provided. The package includes a lead frame, a chip and a sealant. The lead frame has a notch and a plurality of first notch-side leads, a plurality of first notch-side pads, a plurality of second notch-side leads and a plurality of second notch-side pads. The first notch-side leads extend to a first side of the notch. The first notch-side pads are correspondingly disposed on the first notch-side leads. The second notch-side leads extend to a second side of the notch. The second notch-side pads are correspondingly disposed on the second notch-side leads. The sealant seals up the chip and the lead frame and exposes a lower surface of the lead frame. The notch exposes a portion of the sealant.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.