Patent · US Active

Method for fabricating an integrated circuit including memory element with spatially stable material

US8009468B2 · kind B2 · utility

2Cited by

4References

10Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Dieter Andres · Munich, DE
Thomas Happ · Tarrytown, US
Petra Majewski · Munich, DE
Bernhard Ruf · Sauerlach, DE

Key dates

Filing date	Jul 3, 2008
Grant date	Aug 30, 2011
Priority date	—
Expiry date	May 13, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/56
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.