Caching device for NAND flash translation layer
US8010770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2007 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Jun 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.