Error correcting code with chip kill capability and power saving enhancement
US8010875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2007 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Jun 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.