Inventor · Rochester, MN, US

James Anthony Marcella

30Patents
13h-index
98Co-inventors
80Inventor score

Filing activity: Jul 10, 1996 → Apr 30, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US6526469B1 Bus architecture employing varying width uni-directional command bus Physics 133 Expired
US6513091B1 Data routing using status-response signals Physics 103 Expired
US6557069B1 Processor-memory bus architecture for supporting multiple processors Physics 100 Expired
US9081501B2 Multi-petascale highly efficient parallel supercomputer Emerging Cross-Sectional Technologies 85 Active
US6247100A Method and system for transmitting address commands in a multiprocessor system Physics 71 Expired
US6895482B1 Reordering and flushing commands in a computer memory subsystem Physics 53 Expired
US6760856B1 Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration Physics 46 Expired
US6940760B2 Data strobe gating for source synchronous communications interface Physics 41 Expired
US7254663B2 Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes Physics 33 Expired
US6628662B1 Method and system for multilevel arbitration in a non-blocking crossbar switch Electricity 30 Expired
US9971713B2 Multi-petascale highly efficient parallel supercomputer Emerging Cross-Sectional Technologies 22 Active
US6505306B1 Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization Physics 17 Expired
US8010875B2 Error correcting code with chip kill capability and power saving enhancement Physics 15 Active
US7010654B2 Methods and systems for re-ordering commands to access memory Physics 13 Expired
US6671211B2 Data strobe gating for source synchronous communications interface Physics 11 Expired
US7234017B2 Computer system architecture for a processor connected to a high speed bus transceiver Physics 7 Expired
US7873773B2 Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes Physics 7 Active
US6188627A Method and system for improving DRAM subsystem performance using burst refresh control Physics 6 Expired
US6963516B2 Dynamic optimization of latency and bandwidth on DRAM interfaces Physics 4 Expired
US7526692B2 Diagnostic interface architecture for memory device Physics 4 Active
US8108738B2 Data eye monitor method and apparatus Physics 3 Active
US7802158B2 Diagnostic interface architecture for memory device Physics 2 Active
US6185646A Method and apparatus for transferring data on a synchronous multi-drop Physics 1 Expired
US5748919A Shared bus non-sequential data ordering method and apparatus Physics 1 Expired
US6523080B1 Shared bus non-sequential data ordering method and apparatus Physics 1 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.