Patent · US Active

Method and system for implementing efficient locking to facilitate parallel processing of IC designs

US8010917B2 · kind B2 · utility

4Cited by

4References

12Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

David A. Cross · Wrestlingworth, GB
Eric Nequist · Monte Sereno, US

Key dates

Filing date	Dec 26, 2007
Grant date	Aug 30, 2011
Priority date	—
Expiry date	Mar 25, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/30
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.