Patent · US Active

Method and system for placement of electric circuit components in integrated circuit design

US8010925B2 · kind B2 · utility

2Cited by

2References

11Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Markus Buehler · Holzgerlingen, DE
Juergen Koehl · Holzgerlingen, DE

Key dates

Filing date	May 15, 2008
Grant date	Aug 30, 2011
Priority date	—
Expiry date	Jul 17, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement process which arranges the cells in the bins to obtain a legal arrangement while generating simply connected free space for routing channels.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.