Structure for a stacked power clamp having a BigFET gate pull-up circuit
US8010927B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2008 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Dec 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.