Patent · US Active

Method and system for testing bit failures in array elements of an electronic circuit

US8010934B2 · kind B2 · utility

2Cited by

2References

19Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Joachim Kneisel · Stuttgart, DE
Otto A. Torreiter · Echterdingen, DE

Key dates

Filing date	May 28, 2008
Grant date	Aug 30, 2011
Priority date	—
Expiry date	Dec 15, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3171
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write logic of the memory via input signals, building an emulator model (SME) from said changed hardware representation for emulating the array, and injecting errors into the changed hardware representation for determining the array to get stick capabilities.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.