Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US8012797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2009 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Aug 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.