Method of manufacturing layered chip package
US8012802B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 4, 2010 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | May 2, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/928
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.