Vertically stacked pre-packaged integrated circuit chips
US8012803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2010 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Sep 27, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49171
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.