Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device

US8012832B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Mario Giuseppe Saggio · Nettuno, IT
• Ferruccio Frisina · Gravina di Catania, IT
• Simone RASCUNÁ · Catania, IT

Key dates

• Filing date: Jan 8, 2008
• Grant date: Sep 6, 2011
• Expiry date: Jan 8, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393

Abstract

A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by a second implant step with a second implant dose, and forming a surface semiconductor layer. The process also includes forming body regions of the second type of conductivity aligned with the first sub-regions, and carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region aligned and in electric contact with the body regions.