Semiconductor chip substrate with multi-capacitor footprint
US8012874B2 · kind B2 · utility
3Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2007 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Jul 14, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor pads. Each of the plural openings has a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate. A conductor material is placed in the plural openings to establish plural capacitor pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.