Integrated circuit including a stressed dielectric layer with stable stress
US8013372B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2008 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Dec 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed O3 TEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the O3 TEOS oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.