Inventor · Singapore, SG

Wei Lu

26Patents
5h-index
42Co-inventors
69Inventor score

Filing activity: Dec 1, 1995 → Mar 8, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US7271110B2 High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliability Electricity 17 Expired
US5683946A Method for manufacturing fluorinated gate oxide layer Emerging Cross-Sectional Technologies 16 Expired
US7566656B2 Method and apparatus for providing void structures Electricity 12 Active
US7790617B2 Formation of metal silicide layer over copper interconnect for reliability enhancement Electricity 11 Expired
US7892900B2 Integrated circuit system employing sacrificial spacers Electricity 7 Active
US7745320B2 Method for reducing silicide defects in integrated circuits Electricity 5 Active
US9520371B2 Planar passivation for pads Electricity 4 Active
US8354347B2 Method of forming high-k dielectric stop layer for contact hole opening Electricity 4 Active
US9443761B2 Methods for fabricating integrated circuits having device contacts Electricity 4 Active
US9287197B2 Through silicon vias Electricity 3 Active
US9511474B2 CMP head structure with retaining ring Performing Operations; Transporting 2 Active
US9620418B2 Methods for fabricating integrated circuits with improved active regions Electricity 2 Active
US8013372B2 Integrated circuit including a stressed dielectric layer with stable stress Electricity 2 Active
US7855143B2 Interconnect capping layer and method of fabrication Electricity 2 Active
US9437547B2 Through silicon vias Electricity 2 Active
US8264088B2 Planarized passivation layer for semiconductor devices Emerging Cross-Sectional Technologies 2 Active
US9242341B2 CMP head structure Performing Operations; Transporting 2 Active
US7332422B2 Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment Emerging Cross-Sectional Technologies 1 Expired
US9349654B2 Isolation for embedded devices Electricity 1 Active
US9511470B2 CMP head structure with retaining ring Performing Operations; Transporting 0 Active
US7998831B2 Planarized passivation layer for semiconductor devices Emerging Cross-Sectional Technologies 0 Active
US9153473B2 Wafer processing Physics 0 Active
US7960283B2 Method for reducing silicide defects in integrated circuits Electricity 0 Active
US9242338B2 CMP head structure Performing Operations; Transporting 0 Active
US9202746B2 Integrated circuits with improved gap fill dielectric and methods for fabricating same Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.